SH7713 Datasheet, PDF (544/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 14 Timer Unit (TMU)
14.4.3 Interrupt Sources and Priorities
The TMU generates underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the interrupt event
register (INTEVT2) for these interrupts and interrupt processing occurs according to the codes.
The relative priorities of channels can be changed using the interrupt controller (see section 4,
Exception Handling, and section 8, Interrupt Controller (INTC)). Table 14.1 lists TMU interrupt
sources.
Table 14.1 TMU Interrupt Sources
Channel
0
1
2
Interrupt Source
TUNI0
TUNI1
TUNI2
Description
Underflow interrupt 0
Underflow interrupt 1
Underflow interrupt 2
Priority
High
Low
14.5 Usage Notes
14.5.1 Writing to Registers
Synchronization processing is not performed for timer counting during register writes. When
writing to registers, always clear the appropriate start bits for the channel (STR2 to STR0) in
TSTR to halt timer counting.
14.5.2 Reading Registers
Synchronization processing is performed for timer counting during register reads. When timer
counting and register read processing are performed simultaneously, the register value before
TCNT counting down (with synchronization processing) is read.
Rev.1.50 Aug. 30, 2006 Page 504 of 860
REJ09B0288-0150