SH7713 Datasheet, PDF (509/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
0
DE
0
R/W DMA Enable
Enables or disables the DMA transfer. In auto-request
mode, DMA transfer starts by setting the DE bit and DME bit
in DMAOR to 1. In this time, all of the bits TE, NMIF in
DMAOR, and AE in DMAOR must be 0. In an external
request or peripheral module request, DMA transfer starts if
DMA transfer request is generated by the devices or
peripheral modules after setting the bits DE and DME to 1.
In this case, however, all of the bits TE, NMIF, and AE must
be 0 as in the case of auto-request mode. Clearing the DE
bit to 0 can terminate the DMA transfer.
0: DMA transfer disabled
1: DMA transfer enabled
Note: * Only 0 can be written to clear the flag.
13.3.5 DMA Operation Register (DMAOR)
DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the
DMA transfer. This register indicates the DMA transfer status.
DMAOR is initialized to H′0000 at a reset and retains the current value in standby or module
standby mode.
Bit
15 to
10
9
8
Initial
Bit Name Value R/W Description

All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
PR1
0
R/W Priority Mode
PR0
0
R/W Select the priority level between channels when there are
transfer requests for multiple channels simultaneously.
00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5
01: Fixed mode 2: CH0 > CH2 > CH3 > CH1 > CH4 > CH5
10: Reserved (setting prohibited)
11: All channel round-robin mode
Rev.1.50 Aug. 30, 2006 Page 469 of 860
REJ09B0288-0150