SH7713 Datasheet, PDF (659/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Table 17.5 Audio Mode Specification for Transmit Data
Mode
Monaural
Stereo
left and right same audio output
Note: x: Don't care
TDLE
1
1
1
Bit
TDRE
0
1
1
TLREP
x
0
1
Table 17.6 Audio Mode Specification for Receive Data
Bit
Mode
RDLE
RDRE
Monaural
1
0
Stereo
1
1
Note: Left and right same audio mode is not supported in receive data.
Control Data: Control data is written to or read from by the following registers.
• Transmit control data write: SITCR (32-bit access)
• Receive control data read: SIRCR (32-bit access)
Figure 17.6 shows the control data and bit alignment in SITCR and SIRCR.
(a) Control data: one channel
31
24 23
16 15
87
0
Control data
(channel 0)
(b) Control data: two channel
31
24 23
16 15
87
0
Control data
(channel 0)
Control data
(channel 1)
Figure 17.6 Control Data Bit Alignment
The number of channels in control data is specified by CD0E and CD1E bits in SICDAR. Table
17.7 shows the relationship between the number of channels in control data and bit settings. To
use only one channel in control data, use channel 0.
Rev.1.50 Aug. 30, 2006 Page 619 of 860
REJ09B0288-0150