SH7713 Datasheet, PDF (541/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Select operation
Select counter
clock
(1)
Set underflow
interrupt generation ⁽²⁾
Set timer constant
register
(3)
Initialize timer
counter
(4)
Start counting
(5)
Section 14 Timer Unit (TMU)
(1) Select the counter clock
with the TPSC2 to TPSC0
bits in TCR.
(2) Use the UNIE bit in TCR
to set whether to
generate an interrupt
when TCNT underflows.
(3) Set a value in TCOR (the
cycle is the set value plus
1).
(4) Set the initial value in
TCNT.
(5) Set the STR bit in TSTR
to 1 to start operation.
Note: When an interrupt has been generated, clear the flag in the interrupt handler that caused it.
If interrupts are enabled without clearing the flag, another interrupt will be generated.
Figure 14.2 Setting Count Operation
Auto-Reload Count Operation: Figure 14.3 shows the TCNT auto-reload operation.
TCNT value
TCOR
TCOR value set to
TCNT during underflow
H'00000000
STR0–STR2
UNF
Time
Figure 14.3 Auto-Reload Count Operation
Rev.1.50 Aug. 30, 2006 Page 501 of 860
REJ09B0288-0150