SH7713 Datasheet, PDF (710/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Transmit
descriptor
Receive
descriptor
Transmit
buffer
Receive
buffer
External memory
This LSI
Internal bus
External bus
interface
E-DMAC
Internal
bus
interface
Descriptor
Information
Transmit DMAC
Descriptor
Information
Receive DMAC
Transmit
FIFO
Receive
FIFO
EtherC
Figure 19.1 Configuration of E-DMAC, and Descriptors and Buffers
19.2 Register Descriptions
The E-DMAC has the following registers. For addresses and access sizes of these registers, see
section 23, List of Registers.
• E-DMAC mode register (EDMR)
• E-DMAC transmit request register (EDTRR)
• E-DMAC receive request register (EDRRR)
• Transmit descriptor list address register (TDLAR)
• Receive descriptor list address register (RDLAR)
• EtherC/E-DMAC status register (EESR)
• EtherC/E-DMAC status interrupt permission register (EESIPR)
• Transmit/receive status copy enable register (TRSCER)
• Receive missed-frame counter register (RMFCR)
• Transmit FIFO threshold register (TFTR)
• FIFO depth register (FDR)
• Receiving method control register (RMCR)
• E-DMAC operation control register (EDOCR)
• Receive buffer write address register (RBWAR)
• Receive descriptor fetch address register (RDFAR)
• Transmit buffer read address register (TBRAR)
• Transmit descriptor fetch address register (TDFAR)
Rev.1.50 Aug. 30, 2006 Page 670 of 860
REJ09B0288-0150