SH7713 Datasheet, PDF (301/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Program execution state
Interrupt
No
generated?
Yes
No
SR.BL=0
or sleep mode?
Yes
NMI?
No
Yes
Level 15
No
interrupt?
Set interrupt source in
INTEVT, INTEVT2
Save SR to SSR;
save PC to SPC
Set BL/MD/RB
bit in SR to 1
Branch to exception
handler
Yes
Level 14
No
interrupt?
Yes
I3 to I0 level
14 or lower?
Yes
Level 1
No
interrupt?
No
I3 to I0 level
Yes
Yes
13 or lower?
No
Yes
I3 to I0
level 0?
No
I3 to I0: Interrupt mask bits in status register (SR)
Figure 8.3 Interrupt Operation Flowchart
Rev.1.50 Aug. 30, 2006 Page 261 of 860
REJ09B0288-0150