SH7713 Datasheet, PDF (28/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 12.26 Self-Refresh Timing .............................................................................................. 432
Figure 12.27 Access Timing in Low-Frequency Mode .............................................................. 433
Figure 12.28 Access Timing in Power-Down Mode .................................................................. 434
Figure 12.29 Write Timing for SDRAM Mode Register (Based on JEDEC)............................. 437
Figure 12.30 EMRS Command Issue Timing............................................................................. 439
Figure 12.31 Transition Timing in Deep Power-Down Mode.................................................... 440
Figure 12.32 Burst ROM (Clock Asynchronous) Access (Bus Width = 32 Bits,
16-byte Transfer (Number of Bursts = 4), Access Wait for First Time = 2,
Access Wait for 2nd Time and after = 1).............................................................. 442
Figure 12.33 Basic Access Timing for Byte-Selection SRAM (BAS = 0) ................................. 443
Figure 12.34 Basic Access Timing for Byte-Selection SRAM (BAS = 1) ................................. 444
Figure 12.35 Wait Timing for Byte-Selection SRAM (BAS = 1) (Software Wait Only)........... 445
Figure 12.36 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM ............. 446
Figure 12.37 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM ............. 446
Figure 12.38 Example of PCMCIA Interface Connection.......................................................... 448
Figure 12.39 Basic Access Timing for PCMCIA Memory Card Interface................................. 449
Figure 12.40 Wait Timing for PCMCIA Memory Card Interface
(TED[3:0] = B′0010, TEH[3:0] = B′0001, Software Wait = 1,
Hardware Wait = 1) .............................................................................................. 449
Figure 12.41 Example of PCMCIA Space Assignment (CS5BWCR.SA[1:0] = B′10,
CS6BWCR.SA[1:0] = B′10)................................................................................. 450
Figure 12.42 Basic Timing for PCMCIA I/O Card Interface ..................................................... 451
Figure 12.43 Wait Timing for PCMCIA I/O Card Interface (TED[3:0] = B′0010,
TEH[3:0] = B′0001, Software Wait = 1, Hardware Wait = 1) .............................. 452
Figure 12.44 Timing for Dynamic Bus Sizing of PCMCIA I/O Card Interface
(TED[3:0] = B′0010, TEH[3:0] = B′0001, Software Waits = 3) .......................... 452
Figure 12.45 Burst ROM (Clock Synchronous) Access Timing (Burst Length = 8,
Wait Cycles inserted in First Access = 2, Wait Cycles inserted in
Second and Subsequent Accesses = 1).................................................................. 453
Figure 12.46 Bus Arbitration Timing ......................................................................................... 456
Section 13 Direct Memory Access Controller (DMAC)
Figure 13.1 Block Diagram of DMAC ....................................................................................... 460
Figure 13.2 DMA Transfer Flowchart........................................................................................ 476
Figure 13.3 Round-Robin Mode................................................................................................. 480
Figure 13.4 Changes in Channel Priority in Round-Robin Mode............................................... 481
Figure 13.5 Data Flow in Dual Address Mode ........................................................................... 483
Figure 13.6 Example of DMA Transfer Timing in Dual Address Mode
(Source: Ordinary memory, Destination: Ordinary memory) ................................. 484
Figure 13.7 Data Flow in Single Address Mode......................................................................... 485
Figure 13.8 Example of DMA Transfer Timing in Single Address Mode ................................. 486
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