SH7713 Datasheet, PDF (229/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Memory Management Unit (MMU)
results in a physical address space of H'20000000 to H'FFFFFFFF should not be registered in the
TLB.
When the MMU is disabled, masking the upper three bits of the virtual address to 0s creates the
address in the corresponding physical address space. Since this LSI supports 29-bit address space
as physical address space, the upper three bits of the virtual address are ignored as shadow areas.
For details, refer to section 12, Bus State Controller (BSC). For example, address H'00001000 in
the P0 area, address H'80001000 in the P1 area, address H'A0001000 in the P2 area, and address
H'C0001000 in the P3 area are all mapped to the same physical memory. If these addresses are
accessed while the cache is enabled, the upper three bits are always cleared to 0 to guarantee the
continuity of addresses stored in the address array of the cache.
Single Virtual Memory Mode and Multiple Virtual Memory Mode: There are two virtual
memory modes: single virtual memory mode and multiple virtual memory mode. In single virtual
memory mode, multiple processes run in parallel using the virtual address space exclusively and
the physical address corresponding to a given virtual address is specified uniquely. In multiple
virtual memory mode, multiple processes run in parallel sharing the virtual address space, so a
given virtual address may be translated into different physical addresses depending on the process.
By the value set to the MMU control register (MMUCR), either single or multiple virtual mode is
selected.
In terms of operation, the only difference between single virtual memory mode and multiple
virtual memory mode is in the TLB address comparison method (see section 5.3.3, TLB Address
Comparison).
Address Space Identifier (ASID): In multiple virtual memory mode, the address space identifier
(ASID) is used to differentiate between processes running in parallel and sharing virtual address
space. The ASID is eight bits in length and can be set by software setting of the ASID of the
currently running process in page table entry register high (PTEH) within the MMU. When the
process is switched using the ASID, the TLB does not have to be purged.
In single virtual memory mode, the ASID is used to provide memory protection for processes
running simultaneously and using the virtual address space exclusively (see section 5.3.3, TLB
Address Comparison).
5.2 Register Descriptions
There are four registers for MMU processing. These are all peripheral module registers, so they
are located in address space area P4 and can only be accessed from privileged mode by specifying
the address.
Rev.1.50 Aug. 30, 2006 Page 189 of 860
REJ09B0288-0150