SH7713 Datasheet, PDF (518/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
Table 13.4 Selecting External Request Detection with DL, DS Bits
CHCR
DL
DS
0
0
1
1
0
1
Detection of External Request
Low level detection
Falling edge detection
High level detection
Rising edge detection
When DREQ is accepted, the DREQ pin becomes request accept disabled state (non-sensitive
period). After issuing acknowledge signal DACK for the accepted DREQ, the DREQ pin again
becomes request accept enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
Overrun 0: Transfer is aborted after the same number of transfer has been performed as requests.
Overrun 1: Transfer is aborted after transfers have been performed for (the number of requests
plus 1) times.
The DO bit in CHCR selects this overrun 0 or overrun 1.
Table 13.5 Selecting External Request Detection with DO Bit
CHCR
DO
0
1
External Request
Overrun 0
Overrun 1
On-Chip Peripheral Module Request Mode: In this mode, the transfer is performed in response
to the transfer request signal of an on-chip peripheral module.
The DMA transfer request signals comprise the transmit data empty transfer request and receive
data full transfer request from the SCIF0, SCIF1, SIOF0, and SIOF1 set by DMARS0 to
DMARS2.
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0,
NMIF = 0), a transfer is performed upon the input of a transfer request signal. When a transfer
request is set to TXI of the SCIF0, the transfer destination must be the SCIF0’s transmit data
Rev.1.50 Aug. 30, 2006 Page 478 of 860
REJ09B0288-0150