SH7713 Datasheet, PDF (872/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 Electrical Characteristics
SCIFnCK
TxD
(data trans-
mission)
RxD
(data
reception)
RTS
CTS
t_Scyc
t_TXD
t_RTSD
t_RXS t_RXH
t_CTSS t_CTSH
Figure 24.52 SCIF Input/Output Timing in Clock Synchronous Mode
24.3.10 SIOF Module Signal Timing
Table 24.12 SIOF Module Signal Timing
Item
(Conditions: V Q = V Q-RTC = 3.0 to 3.6 V, V = V -PLL1 = V -PLL2 = 1.4 to 1.6 V,
CC
CC
CC
CC
CC
V_SSQ = V_SS = V_SSQ-RTC = V_SS-PLL1 = V_SS-PLL2 = 0 V, T_a = –20 to 75°C)
Symbol Min.
Max. Unit Figure
SIOMCLK clock input cycle time t
30
—
Mcyc
SIOMCLK input high-level width t
MWH
0.4
×
t
Mcyc
—
SIOMCLK input low-level width
t_MWL
0.4 × t_Mcyc
—
SCK_SIO clock cycle time
t_SIcyc
2 × t_Pcyc
—
SCK_SIO output high-level width t_SWHO
0.4 × t_SIcyc
—
SCK_SIO output low-level width
t_SWLO
0.4 × t_SIcyc
—
SIOFSYNC output delay time
t_FSD
—
20
SCK_SIO input high-level width
t
SWHI
0.4
×
t
SIcyc
—
SCK_SIO input low-level width
t
SWLI
0.4
×
t
SIcyc
—
SIOFSYNC input setup time
t
20
—
FSS
SIOFSYNC input hold time
t
20
—
FSH
TXD_SIO output delay time
t_STDD
—
20
RXD_SIO input setup time
t_SRDS
20
—
RXD_SIO input hold time
t_SRDH
20
—
Note:
t
Pcyc
is
the
cycle
time
(ns)
of
the
peripheral
clock
(Pφ).
ns 24.53
24.54 to 24.58
24.54 to 24.57
24.58
24.54 to 24.58
Rev.1.50 Aug. 30, 2006 Page 832 of 860
REJ09B0288-0150