SH7713 Datasheet, PDF (297/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Bit
Bit Name Initial Value R/W Description
2

0
R
Reserved
1

0
R
This bit is always read as 0. The write value
should always be 0.
0
EINT0R
0
R
EINT0 Interrupt Request
Indicates whether the EINT0 (E-DMAC) interrupt
request is generated.
0: EINT0 interrupt request is not generated
1: EINT0 interrupt request is generated
8.4.10 Interrupt Request Register 7 (IRR7)
IRR7 is an 8-bit register that indicates whether an interrupt request from the SIOF0 is generated.
This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in
standby mode.
Bit
Bit Name Initial Value R/W Description
7
CCI0R
0
R
CCI0 Interrupt Request
Indicates whether the CCI0 (SIOF0) interrupt
request is generated.
0: CCI0 interrupt request is not generated
1: CCI0 interrupt request is generated
6
RXI0R
0
R
RXI0 Interrupt Request
Indicates whether the RXI0 (SIOF0) interrupt
request is generated.
0: RXI0 interrupt request is not generated
1: RXI0 interrupt request is generated
Rev.1.50 Aug. 30, 2006 Page 257 of 860
REJ09B0288-0150