SH7713 Datasheet, PDF (124/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
• Example 7: Repeat loop consisting of two instructions (extended to the instruction stream
shown in example 3, above)
REPEAT RptStart, RptEnd, #4
instr0
;
RptStart: instr1
; [Repeat start instruction]
RptEnd: instr2
; [Repeat end instruction]
• Example 8: Repeat loop consisting of one instruction instructions (extended to the instruction
stream shown in example 4, above)
REPEAT RptStart, RptEnd, #4
instr0
;
RptStart:
RptEnd: instr1
; [Repeat start instruction] ==
[Repeat end instruction]
In the DSP mode, the system control instructions (LDC and STC) that handle the RS and RE
registers are extended. The RC[11:0] bits and RF[1:0] bits of the SR can be controlled by the LDC
and STC instructions for the SR register. These instructions should be used if an exception is
enabled during repeat loop execution. The repeat loop can be resumed correctly by storing the RS
and RE register values and RC[11:0] bits and RF[1:0] bits of the SR register before exception
handling and by restoring the stored values after exception handling. However, note that there are
some restrictions on exception acceptance during repeat loop execution. For details refer to
Restrictions on Repeat Loop Control in section 3.3.1, Repeat Control Instructions and section 4,
Exception Handling.
Table 3.6 DSP Mode Extended System Control Instructions
Instruction
STC RS, Rn
STC RE, Rn
STC.L RS, @-Rn
STC.L RE, @-Rn
LDC.L @Rn+, RS
LDC.L @Rn+, RE
LDC Rn,RS
LDC Rn, RE
Operation
RS→Rn
RE→Rn
Rn-4→Rn, RS→(Rn)
Rn-4→Rn, RE→(Rn)
(Rn)→RS, Rn+4→Rn
(Rn)→RE, Rn+4→Rn
Rn →RS
Rn→RE
Number of
Execution States
1
1
1
1
4
4
4
4
Rev.1.50 Aug. 30, 2006 Page 84 of 860
REJ09B0288-0150