SH7713 Datasheet, PDF (757/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.4 Usage Notes
19.4.1 Using of EDTRR and EDRRR
(1) Phenomenon
If the transmit and receive descriptor active bit has the “inactive” setting, the EDTRR register: TR
bit (Transmit Request) and the EDRRR register: RR bit (Receive Request) are cleared and the
operation of transmit E-DMAC is halted.
When the timing of clear TR/RR request bit and set TR/RR request bit by user’s firmware are
matched, E-DMAC cannot recognize the exact condition of TR/RR bit.
(2) Condition
When TR/RR request bit is always set by the firmware without checking the state of TR/RR
request bit.
(3) Countermeasures
Please check the TR/RR request bit is cleared by E-DMAC first, and then set the TR/RR request
bit by user’s firmware.
1. There are two ways to check TR request bit that is cleared by E-DMAC.
• Possible to check read “0” of TR bit of E-DMAC directly.
• Possible to check read “1” of TDE (Transmit Descriptor Exhausted) in EESR resister after the
interrupt on.
2. There are two ways to check RR request bit that is cleared by E-DMAC.
• Possible to check read “0” of RR bit of E-DMAC directly.
• Possible to check read “1” of RDE (Receive Descriptor Exhausted) in EESR resister after
interrupt on.
Rev.1.50 Aug. 30, 2006 Page 717 of 860
REJ09B0288-0150