SH7713 Datasheet, PDF (502/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
13.3 Register Descriptions
The DMAC has the following registers. Refer to section 23, List of Registers, for the addresses
and access size of these registers.
Channel 0:
• DMA source address register_0 (SAR_0)
• DMA destination address register_0 (DAR_0)
• DMA transfer count register_0 (DMATCR_0)
• DMA channel control register_0 (CHCR_0)
Channel 1:
• DMA source address register_1 (SAR_1)
• DMA destination address register_1 (DAR_1)
• DMA transfer count register_1 (DMATCR_1)
• DMA channel control register _1 (CHCR_1)
Channel 2:
• DMA source address register_2 (SAR_2)
• DMA destination address register_2 (DAR_2)
• DMA transfer count register_2 (DMATCR_2)
• DMA channel control register_2 (CHCR_2)
Channel 3:
• DMA source address register_3 (SAR_3)
• DMA destination address register_3 (DAR_3)
• DMA transfer count register_3 (DMATCR_3)
• DMA channel control register_3 (CHCR_3)
Channel 4:
• DMA source address register_4 (SAR_4)
• DMA destination address register_4 (DAR_4)
• DMA transfer count register_4 (DMATCR_4)
• DMA channel control register_4 (CHCR_4)
Rev.1.50 Aug. 30, 2006 Page 462 of 860
REJ09B0288-0150