SH7713 Datasheet, PDF (503/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
Channel 5:
• DMA source address register_5 (SAR_5)
• DMA destination address register_5 (DAR_5)
• DMA transfer count register_5 (DMATCR_5)
• DMA channel control register_5 (CHCR_5)
Common:
• DMA operation register (DMAOR)
• DMA extension resource selector 0 (DMARS0)
• DMA extension resource selector 1 (DMARS1)
• DMA extension resource selector 2 (DMARS2)
13.3.1 DMA Source Address Register (SAR)
SAR is a 32-bit readable/writable register that specifies the source address of a DMA transfer.
During a DMA transfer, SAR indicates the next source address. When the data is transferred from
an external device with the DACK in single address mode, SAR is ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the
source address value.
SAR is undefined at reset and retains the current value in standby or module standby mode.
13.3.2 DMA Destination Address Register (DAR)
DAR is a 32-bit readable/writable register that specifies the destination address of a DMA transfer.
During a DMA transfer, DAR indicates the next destination address. When the data is transferred
to an external device with the DACK in single address mode, DAR is ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the
source address value.
DAR is undefined at reset and retains the current value in standby or module standby mode.
Rev.1.50 Aug. 30, 2006 Page 463 of 860
REJ09B0288-0150