SH7713 Datasheet, PDF (573/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Module data bus
RxDn
TxDn
SCIFnCK
SCFRDR_n
(16-stage)
SCRSR_n
SCFTDR_n
(16-stage)
SCTSR_n
SCSMR_n
SCLSR_n
SCFDR_n
SCFCR_n
SCFSR_n
SCSCR_n
SCBRR_n
Baud rate
generator
Transmission/
reception control
Parity generation
Parity check
Clock
External clock
CTSn
RTSn
[Legend]
SCRSR_n: Receive shift register
SCFRDR_n: Receive FIFO data register
SCTSR_n: Transmit shift register
SCFTDR_n: Transmit FIFO data register
SCSMR_n: Serial mode register
SCSCR_n: Serial control register
SCIFn
SCFSR_n: Serial status register
SCBRR_n: Bit rate register
SCFCR_n: FIFO control register
SCFDR_n: FIFO data count register
SCLSR_n: Line status register
n:
0, 1
Figure 16.1 Block Diagram of SCIF
Internal
data bus
Pφ
Pφ/4
Pφ/16
Pφ/64
TXIn
RXIn
ERIn
BRIn
Rev.1.50 Aug. 30, 2006 Page 533 of 860
REJ09B0288-0150