SH7713 Datasheet, PDF (687/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.6 MAC Address High Register (MAHR)
MAHR is a 32 -bit readable/writable register that specifies the upper 32 bits of the 48-bit MAC
address. The settings in this register are normally made in the initialization process after a reset.
The MAC address setting must not be changed while the transmitting and receiving functions are
enabled. To switch the MAC address setting, return the EtherC and E-DMAC to their initial states
by means of the SWR bit in EDMR before making settings again.
Initial
Bit
Bit Name Value
31 to 0 MA47 to All 0
MA16
R/W Description
R/W MAC Address Bits
These bits are used to set the upper 32 bits of the
MAC address.
If the MAC address is 01-23-45-67-89-AB
(hexadecimal), the value set in this register is
H'01234567.
18.3.7 MAC Address Low Register (MALR)
MALR is a 32-bit readable/writable register that specifies the lower 16 bits of the 48-bit MAC
address. The settings in this register are normally made in the initialization process after a reset.
The MAC address setting must not be changed while the transmitting and receiving functions are
enabled. To switch the MAC address setting, return the EtherC and E-DMAC to their initial states
by means of the SWR bit in EDMR before making settings again.
Initial
Bit
Bit Name Value R/W
31 to 16 
All 0
R
15 to 0 MA15 to All 0
R/W
MA0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
MAC Address Bits 15 to 0
These bits are used to set the lower 16 bits of the MAC
address.
If the MAC address is 01-23-45-67-89-AB
(hexadecimal), the value set in this register is
H'000089AB.
Rev.1.50 Aug. 30, 2006 Page 647 of 860
REJ09B0288-0150