SH7713 Datasheet, PDF (446/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Table 12.13 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (2)-2
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 bits) 01 (12 bits) 10 (10 bits)
Output Pin of Row Address Column Address Synchronous
This LSI
Output
Output
DRAM Pin
A17
A27
A17
A16
A26
A16
A15
A25*²
A25*²
A14
A24*²
A24*²
A13 (BA1)
A12 (BA0)
A13
A23
A13
A11
A12
A22
L/H*¹
A10/AP
A11
A21
A11
A9
A10
A20
A10
A8
A9
A19
A9
A7
A8
A18
A8
A6
A7
A17
A7
A5
A6
A16
A6
A4
A5
A15
A5
A3
A4
A14
A4
A2
A3
A13
A3
A1
Function
Unused
Specifies bank
Address
Specifies
address/precharge
Address
Rev.1.50 Aug. 30, 2006 Page 406 of 860
REJ09B0288-0150