SH7713 Datasheet, PDF (249/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Memory Management Unit (MMU)
5.5.5 MMU Exception in Repeat Loop
If a CPU address error or MMU exception occurs in a specific instruction in the repeat loop, the
SPC may indicate an illegal address or the repeat loop cannot be reexecuted correctly even if the
SPC is correct. Accordingly, if a CPU address error or MMU exception occurs in a specific
instruction in the repeat loop, this LSI generates a specific exception code to set the EXPEVT to
H’070 for a TLB miss exception, TLB invalid exception, initial page write exception, and CPU
address error and to H’0D0 for a TLB protection violation exception. In addition, a vector offset
for TLB miss exception is H’100. For details, refer to section 4.4.3, Exception in Repeat Control
Period.
Rev.1.50 Aug. 30, 2006 Page 209 of 860
REJ09B0288-0150