SH7713 Datasheet, PDF (677/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
Section 18 Ethernet Controller (EtherC)
This LSI has an on-chip Ethernet controller (EtherC) conforming to the Ethernet or the IEEE802.3
MAC (Media Access Control) layer standard. Connecting a physical-layer LSI (PHY-LSI)
complying with this standard enables the Ethernet controller (EtherC) to perform transmission and
reception of Ethernet/IEEE802.3 frames. The LSI has one MAC layer interface port which can be
made to perform transmission and reception independently. The Ethernet controller is connected
to the Ethernet Direct Memory Access Controller (E-DMAC) for Ethernet controller inside the
LSI, and carries out high-speed data transfer to and from the memory.
Figure 18.1 shows a configuration of the EtherC.
18.1 Features
• Transmission and reception of Ethernet/IEEE802.3 frames
• Supports 10/100 Mbps receive/transfer
• Supports full-duplex and half-duplex modes
• Conforms to IEEE802.3u standard MII (Media Independent Interface)
• Magic Packet detection and Wake-On-LAN (WOL) signal output
Ether C
E-DMAC
E-DMAC Interface
MAC
Command status
interface
Receive
controller
MII
Transmit
controller
PHY
Figure 18.1 Configuration of EtherC
ISFETH01B_000020020900
Rev.1.50 Aug. 30, 2006 Page 637 of 860
REJ09B0288-0150