SH7713 Datasheet, PDF (22/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

18.4.6 Operation by IPG Setting...................................................................................... 666
18.5 Connection to LSI.............................................................................................................. 667
18.6 Usage Notes ....................................................................................................................... 668
18.6.1 Initial Setting ........................................................................................................ 668
Section 19 Ethernet Controller Direct Memory Access Controller
(E-DMAC)....................................................................................... 669
19.1 Features.............................................................................................................................. 669
19.2 Register Descriptions......................................................................................................... 670
19.2.1 E-DMAC Mode Register (EDMR)....................................................................... 671
19.2.2 E-DMAC Transmit Request Register (EDTRR) .................................................. 672
19.2.3 E-DMAC Receive Request Register (EDRRR).................................................... 673
19.2.4 Transmit Descriptor List Address Register (TDLAR).......................................... 674
19.2.5 Receive Descriptor List Address Register (RDLAR) ........................................... 675
19.2.6 EtherC/E-DMAC Status Register (EESR)............................................................ 675
19.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)....................... 681
19.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................. 684
19.2.9 Receive Missed-Frame Counter Register (RMFCR) ............................................ 685
19.2.10 Transmit FIFO Threshold Register (TFTR).......................................................... 686
19.2.11 FIFO Depth Register (FDR) ................................................................................. 688
19.2.12 Receiving Method Control Register (RMCR) ...................................................... 689
19.2.13 E-DMAC Operation Control Register (EDOCR) ................................................. 690
19.2.14 Receive Buffer Write Address Register (RBWAR).............................................. 691
19.2.15 Receive Descriptor Fetch Address Register (RDFAR)......................................... 691
19.2.16 Transmit Buffer Read Address Register (TBRAR) .............................................. 691
19.2.17 Transmit Descriptor Fetch Address Register (TDFAR) ....................................... 692
19.2.18 Overflow Alert FIFO Threshold Register (FCFTR) ............................................. 692
19.2.19 Transmit Interrupt Register (TRIMD) .................................................................. 694
19.3 Operation ........................................................................................................................... 694
19.3.1 Descriptors and Descriptor List ............................................................................ 695
19.3.2 Transmission......................................................................................................... 708
19.3.3 Reception .............................................................................................................. 710
19.3.4 Transmit/Receive Processing of Multi-Buffer Frame
(Single-Frame/ Multi-Descriptor)......................................................................... 712
19.3.5 Receive FIFO Overflow Alert Signal (ARBUSY)................................................ 714
19.4 Usage Notes ....................................................................................................................... 717
19.4.1 Using of EDTRR and EDRRR ............................................................................. 717
19.4.2 Endian Support in E-DMAC................................................................................. 718
Rev.1.50 Aug. 30, 2006 Page xxii of xl