SH7713 Datasheet, PDF (153/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
PADD A0, M0, A0
DCF PINC M1, A1
PCMP M1, M0
PMULS X0, Y0, M0
MOVX.W @R4+, X0
MOVX.W @R5+R8, X0
MOVX.W @R4, X1
MOVY.W @R6+, Y0
MOVY.W @R7+, Y1
[NOPY]
Figure 3.6 Sample Parallel Instruction Program
[ ] mean that the contents can be omitted.
The no operation instructions NOPX and NOPY can be omitted. For details on the B field in DSP
data operation instructions, refer to section 3.6.4, DSP Operation Instructions.
The DSR register condition code bit (DC) is always updated on the basis of the result of an
unconditional ALU or shift operation instruction. Conditional instructions do not update the DC
bit. Multiply instructions, also, do not update the DC bit. DC bit updating is performed by means
of the CS[2:0] bits in the DSR register. The DC bit update rules are shown in table 3.19.
Rev.1.50 Aug. 30, 2006 Page 113 of 860
REJ09B0288-0150