SH7713 Datasheet, PDF (406/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
• CS4WCR
Bit
31 to
21
Initial
Bit Name Value R/W

All 0 R
20
BEN
0
R/W
19, 18 
All 0 R
17
BW1
0
R/W
16
BW0
0
R/W
15 to 
13
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Burst Enable Specification
Enables or disables 8-burst access for a 16-bit bus width
or 16- burst access for an 8-bit bus width during 16-byte
access. If this bit is set to 1, 2-burst access is performed
four times when the bus width is 16 bits and 4-burst
access is performed four times when the bus width is 8
bits.
To use a device that does not support 8-burst access or
16-burst access, set this bit to 1.
0: Enables 8-burst access for a 16-bit bus width and 16-
burst access for an 8-bit bus width.
1: Disables 8-burst access for a 16-bit bus width and 16-
burst access for an 8-bit bus width.
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted between
the second or later access cycles in burst access.
00: 0 cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev.1.50 Aug. 30, 2006 Page 366 of 860
REJ09B0288-0150