SH7713 Datasheet, PDF (183/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
3.6.3 Single-Data Transfer Instructions
Table 3.37 Single Data Transfer Instructions
Instruction
Instruction Code Operation
Execu-
tion
States DC Category
MOVS.W @-As,Ds 111101AADDDD0000 As-2 → As, (As) → MSW of Ds, 1

0 → LSW of Ds
MOVS.W @As,Ds
111101AADDDD0100 (As) → MSW of Ds, 0 → LSW 1

of Ds
MOVS.W @As + ,Ds 111101AADDDD1000 (As) → MSW of Ds, 0 → LSW 1

of Ds, As + 2 → As
MOVS.W @As + Ix,Ds 111101AADDDD1100 (As) → MSW of Ds, 0 → LSW 1

of Ds, As + Ix → As
MOVS.W Ds,@-As 111101AADDDD0001 As-2 → As, MSW of Ds → (As) 1
*
MOVS.W Ds,@As
111101AADDDD0101 MSW of Ds → (As)
1
*
MOVS.W Ds,@As + 111101AADDDD1001 MSW of Ds → (As), As + 2 →As 1
*
MOVS.W Ds,@As + Ix 111101AADDDD1101 MSW of Ds → (As),
As + Ix → As
1
*
MOVS.L @-As,Ds
111101AADDDD0010 As-4 → As, (As) → Ds
1

MOVS.L @As,Ds
111101AADDDD0110 (As) → Ds
1

MOVS.L @As + ,Ds 111101AADDDD1010 (As) → Ds, As + 4 → As
1

MOVS.L @As + Ix,Ds 111101AADDDD1110 (As) → Ds, As + Ix → As
1

MOVS.L Ds,@-As
111101AADDDD0011 As-4 → As, Ds → (As)
1

MOVS.L Ds,@As
111101AADDDD0111 Ds → (As)
1

MOVS.L Ds,@As + 111101AADDDD1011 Ds → (As), As + 4 → As
1

MOVS.L Ds,@As + Ix 111101AADDDD1111 Ds → (As), As + Ix → As
1

Note: * If guard bit registers A0G and A1G are specified in source operand Ds, the data is
output to the LDB[7:0] bus and the sign bit is copied into the upper bits, [31:8].
The correspondence between DSP data transfer operands and registers is shown in table 3.38.
Rev.1.50 Aug. 30, 2006 Page 143 of 860
REJ09B0288-0150