SH7713 Datasheet, PDF (732/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.2.17 Transmit Descriptor Fetch Address Register (TDFAR)
TDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor
information from the transmission descriptor. Which transmission descriptor information is used
for processing by the E-DMAC can be recognized by monitoring addresses displayed in this
register. The address from which the E-DMAC is actually fetching a descriptor may be different
from the value read from this register.
Initial
Bit
Bit Name Value R/W Description
31 to 0 TDFA31 to All 0
R
TDFA0
Transmission-Descriptor Fetch Address
These bits can only be read. Writing is prohibited.
19.2.18 Overflow Alert FIFO Threshold Register (FCFTR)
FCFTR is a 32-bit readable/writable register that sets the flow control of the EtherC. The threshold
can be specified by the size of the receive FIFO data (RFD2 to RFD0) and the number of receive
frames (RFF2 to RFF0).
If the same receive FIFO size as set by the FIFO size register (FDR) is set when flow control is
turned on according to the RFD setting condition, flow control is turned on with (FIFO data size −
64) bytes. For instance, when RFD in FDR = 7 and RFD in FCFTR = 7, flow control is turned on
when (2048 − 64) bytes of data is stored in the receive FIFO. The value set in the RFD bits in this
register should be equal to or less than those in FDR.
Flow control is turned on when any of the setting conditions of the RFF2 to RFF0 bits or the
RFD2 to RFD0 bits is satisfied. Flow control is turned off when none of the conditions is satisfied
(release).
Rev.1.50 Aug. 30, 2006 Page 692 of 860
REJ09B0288-0150