SH7713 Datasheet, PDF (646/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Initial
Bit Bit Name Value R/W Description
1
RFUDR 0
R/W Receive FIFO Underrun
Receive FIFO underrun means that reading of SIRDR has
occurred when the receive FIFO is empty. When a receive
underrun occurs, the value of data read from SIRDR is not
guaranteed.
This bit is valid when the RXE bit in SICTR is 1. When 1 is
written to this bit, the contents are cleared. If the issue of
interrupts by this bit is enabled, the SIOF issues an error
interrupt.
0: No receive FIFO underrun
1: Receive FIFO underrun
0
RFOVR 0
R/W Receive FIFO Overrun
Receive FIFO overrun means that writing has occurred
when the receive FIFO is full. When a receive overrun
occurs, the SIOF indicates the overrun, and receive data is
lost.
This bit is valid when the RXE bit in SICTR is 1. When 1 is
written to this bit, the contents are cleared. If the issue of
interrupts by this bit is enabled, the SIOF issues an error
interrupt.
0: No receive FIFO overrun
1: Receive FIFO overrun
Rev.1.50 Aug. 30, 2006 Page 606 of 860
REJ09B0288-0150