SH7713 Datasheet, PDF (688/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.8 Receive Frame Length Register (RFLR)
RFLR is a 32-bit readable/writable register and it specifies the maximum frame length (in bytes)
that can be received by this LSI. The settings in this register must not be changed while the
receiving function is enabled.
Initial
Bit
Bit Name Value R/W
31 to 12 
All 0
R
11 to 0 RFL11 to All 0
R/W
RFL0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Receive Frame Length 11 to 0
The frame length described here refers to all fields
from the destination address up to the CRC data.
Frame contents from the destination address up to the
data are actually transferred to memory. CRC data is
not included in the transfer.
When data that exceeds the specified value is
received, the part of the data that exceeds the
specified value is discarded.
H’000 to H’5EE: 1,518 bytes
H’5EF: 1,519 bytes
H’5F0: 1,520 bytes
::
::
H’7FF: 2,047 bytes
H’800 to H’FFF: 2,048 bytes
Rev.1.50 Aug. 30, 2006 Page 648 of 860
REJ09B0288-0150