SH7713 Datasheet, PDF (160/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Operation Sequence Example
MOVX.W @(R4, R8), X0
PADD X0, Y0, A0 MOVX.W @R4+, X0
Slot
Stage
1
2
3
4
5
6
IF
MOVX MOVX & PADD
ID
EX
MA/DSP
MOVX
MOVX & PADD
Addressing Addressing
MOVX MOVX & PADD
Previous cycle result is used.
Figure 3.10 Operation Sequence Example
Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. However, in case of a conditional
operation, they are not updated even though the specified condition is true and the operation is
executed. In case of an unconditional operation, they are always updated in accordance with the
operation result. The definition of a DC bit is selected by CS[2:0] (condition selection) bits in
DSR. The DC bit result is as follows:
Carry or Borrow Mode: CS[2:0] = 000: The DC bit indicates that carry or borrow is generated
from the most significant bit of the operation result, except the guard-bit parts. Some examples are
shown in figure 3.11. This mode is the default condition. When the input data is negative in a
PABS or PNEG instruction, carry is generated.
Rev.1.50 Aug. 30, 2006 Page 120 of 860
REJ09B0288-0150