SH7713 Datasheet, PDF (483/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
CKIO
A25 to A0
CSn
WEn(BEn)
T1
T2
RD/WR
Read
RD
D31 to D0
RD/WR
Write
RD
High
D31 to D0
BS
DACKn*
Note: The waveform for DACKn is when active low is specified.
Figure 12.33 Basic Access Timing for Byte-Selection SRAM (BAS = 0)
Rev.1.50 Aug. 30, 2006 Page 443 of 860
REJ09B0288-0150