SH7713 Datasheet, PDF (755/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(1) Operation of Receive FIFO Overflow Alert Signal
Receive FIFO overflow alert signal is asserted when the number of the receive data accumulated
in the receive FIFO is equal to or more than the threshold set in the overflow alert FIFO threshold
register (FCFTR) (1). After that, when the number of the accumulated receive data drops below
(threshold − 32) bytes, the signal is negated (2).
Here, threshold values are as follows: 2048 − 64, 1792 − 32,…. Therefore, the signal-negated
values are as follows: 2048 − 96, 1792 − 64,….
Receive
FIFO
full
Receive
data
Threshold
(threshold − 32) bytes
(1)
(2)
empty
Alert signal
Transfer to memory by E-DMAC
t
Figure 19.9 Summary of Receive FIFO Overflow Alert Signal
(2) Receive FIFO Overflow Alert Signal Changing
The receive FIFO in the E-DMAC can perform writing (reception) data from the Ethernet line and
reading data from the system simultaneously. Therefore during system operation, receive data of
FIFO is always increased or decreased. If the change is performed near the threshold, the receive
FIFO overflow alert signal may be seen as shown in figure 19.10. Minimum of receive data
changes depending on the number of FIFO read cycles and rate of Ethernet line (10 to 100 Mbs).
Rev.1.50 Aug. 30, 2006 Page 715 of 860
REJ09B0288-0150