SH7713 Datasheet, PDF (644/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Initial
Bit Bit Name Value R/W
11
—
0
R
10
RCRDY 0
R
9
RFFUL 0
R
8
RDREQ 0
R
7 to 5 —
All 0 R
Description
Reserved
This bit is always read as 0. The write value should always
be 0.
Receive Control Data Ready
This bit indicates a state of the SIOF. If SIRCR is read, the
SIOF clears this bit. This bit is valid when the RXE bit in
SICTR is set to 1. If the issue of interrupts by this bit is
enabled, the SIOF issues a control interrupt. If SIRCR is
written when this bit is set to 1, SIRCR is modified by the
latest data.
0: Indicates that SIRCR stores no valid data
1: Indicates that SIRCR stores valid data
Receive FIFO Full
This bit indicates a state. If SIRDR is read, the SIOF clears
this bit. This bit is valid when the RXE bit in SICTR is 1. If
the issue of interrupts by this bit is enabled, the SIOF
issues a control interrupt.
0: Receive FIFO not full
1: Receive FIFO full
Receive Data Transfer Request
A receive data transfer request is issued when the valid
space in the receive FIFO exceeds the size specified by the
RFWM bit in SIFCTR.
This bit is valid when the RXE bit in SICTR is 1. This bit
indicates a state the SIOF. If the size of valid space in the
receive FIFO is less than the size specified by the RFWM
bit in SIFCTR, the SIOF clears this bit.
If the issue of interrupts by this bit is enabled, the SIOF
issues a receive interrupt.
0: Indicates that the size of valid space in the receive FIFO
does not exceed the size specified by the RFWM bit in
SIFCTR.
1: Indicates that the size of valid space in the receive FIFO
exceeds the size specified by the RFWM bit in SIFCTR.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev.1.50 Aug. 30, 2006 Page 604 of 860
REJ09B0288-0150