SH7713 Datasheet, PDF (217/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
Note:
In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
detection instructions and all the remaining instructions. In a repeat loop consisting of four
or more instructions, restrictions apply to only the three instructions that include a repeat
end instruction.
Exception Retained in Repeat Control Period: In the repeat control period, an interrupt or some
exception will be retained to prevent an exception acceptance at an instruction where returning
from the exception cannot be performed correctly. For details, refer to repeat loop program
examples 1 to 4. In the examples, exceptions generated at instructions indicated as [B], [C], [C1],
or [C2], the following processing is executed.
• Interrupt, DMA address error
An exception request is not accepted and retained at instructions [B] and [C]. If an instruction
indicates as [A] is executed at the next time, an exception request is accepted.* As shown in
program examples 1 to 4, any interrupt or DMA address error cannot be accepted in a repeat
loop consisting of four instructions or less.
Note: * An interrupt request or a DMA address error exception request is retained in the
interrupt controller (INTC) and the direct memory access controller (DMAC) until the
CPU can accept a request.
• User break before instruction execution
A user break before instruction execution is accepted at instruction [B], and an address of
instruction [B] is saved in the SPC. This exception cannot be accepted at instruction [C] but
the exception request is retained until an instruction [A] or [B] is executed at the next time.
Then, the exception request is accepted before an instruction [A] or [B] is executed. In this
case, an address of instruction [A] or [B] is saved in the SPC.
• User break after instruction execution
A user break after instruction execution cannot be accepted at instructions [B] and [C] but the
exception request is retained until an instruction [A] or [B] is executed at the next time. Then,
the exception request is accepted before an instruction [A] or [B] is executed. In this case, an
address of instruction [A] or [B] is saved in the SPC.
Table 4.4 Exception Acceptance in Repeat Loop
Exception Type
Interrupt
DMA address error
User break before instruction execution
User break after instruction execution
Instruction [B]
Not accepted
Not accepted
Accepted
Not accepted
Instruction [C]
Not accepted
Not accepted
Not accepted
Not accepted
Rev.1.50 Aug. 30, 2006 Page 177 of 860
REJ09B0288-0150