SH7713 Datasheet, PDF (609/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
ER = 1?
Yes
Receive error handling
1. Whether a framing error or parity error has
occurred in the receive data read from
SCFRDR can be ascertained from the FER
and PER bits in SCFSR.
2. When a break signal is received, receive
data is not transferred to SCFRDR while
the BRK flag is set. However, note that the
last data in SCFRDR is H'00 and the break
data in which a framing error occurred is
stored.
No
BRK = 1?
Yes
Break handling
No
DR = 1?
Yes
Read receive data in SCFRDR
Clear DR, ER, and BRK flags
in SCFSR and ORER flag
in SCLSR to 0
End
Figure 16.7 Sample Serial Reception Flowchart (2)
Rev.1.50 Aug. 30, 2006 Page 569 of 860
REJ09B0288-0150