SH7713 Datasheet, PDF (475/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is written in a byte-
size access to the addresses shown in table 12.19. In this time 0 is output at the external address
pins of A12 or later.
Table 12.19 Access Address in SDRAM Mode Register Write
• Setting for Area 2 (SDMR2)
Burst read/single write (burst length 1):
Data Bus Width
16 bits
32 bits
CAS Latency
2
3
2
3
Access Address
H′A4FD4440
H′A4FD4460
H′A4FD4880
H′A4FD48C0
External Address Pin
H′0000440
H′0000460
H′0000880
H′00008C0
Burst read/burst write (burst length 1):
Data Bus Width
16 bits
32 bits
CAS Latency
2
3
2
3
Access Address
H′A4FD4040
H′A4FD4060
H′A4FD4080
H′A4FD40C0
External Address Pin
H′0000040
H′0000060
H′0000080
H′00000C0
• Setting for Area 3 (SDMR3)
Burst read/single write (burst length 1):
Data Bus Width
16 bits
32 bits
CAS Latency
2
3
2
3
Access Address
H′A4FD5440
H′A4FD5460
H′A4FD5880
H′A4FD58C0
External Address Pin
H′0000440
H′0000460
H′0000880
H′00008C0
Rev.1.50 Aug. 30, 2006 Page 435 of 860
REJ09B0288-0150