SH7713 Datasheet, PDF (159/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Table 3.21 Variation of ALU Fixed-Point Operations
Mnemonic
PADD
PSUB
PADDC
PSUBC
PCMP
PCOPY
PABS
PNEG
PCLR
Function
Addition
Subtraction
Addition with carry
Subtraction with borrow
Comparison
Data copy
Absolute
Negation
Clear
Source 1
Sx
Sx
Sx
Sx
Sx
Sx
All 0
Sx
All 0
Sx
All 0
All 0
Source 2
Sy
Sy
Sy
Sy
Sy
All 0
Sy
All 0
Sy
All 0
Sy
All 0
Destination
Dz (Du)
Dz (Du)
Dz
Dz
—
Dz
Dz
Dz
Dz
Dz
Dz
Dz
Table 3.22 Correspondence between Operands and Registers
Register
A0
A1
M0
M1
X0
X1
Y0
Y1
Sx
Sy
Dz
Du
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
As shown in figure 3.10, data loaded from the memory at the MA stage, which is programmed at
the same line as the ALU operation, is not used as a source operand for this operation, even
though the destination operand of the data load operation is identical to the source operand of the
ALU operation. In this case, previous operation results are used as the source operands for the
ALU operation, and then updated as the destination operand of the data load operation.
Rev.1.50 Aug. 30, 2006 Page 119 of 860
REJ09B0288-0150