SH7713 Datasheet, PDF (666/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
No.
Time Chart
Start
1
Set SIMDR, SISCR, SITDAR,
SIRDAR, SICDAR, and SIFCTR
2
Set TXE bit in SICTR to 1
3
No
TDREQ=1?
Yes
4
Set SITDR
SIOF Settings
SIOF Operation
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and the upper limit value of FIFO
request
Set to enable transmission
Submit transmission request
to disable transmission
when frame synchronous
signal is transmitted
Set transmit data
5
Output SITDR contents from TXD_SIO
synchronously with SIOFSYNC
Transmit
Transfer
No
ended?
Yes
6
Clear TXE bit in SICTR to 0
End
Set to disable transmission
End transmission
Figure 17.11 Example of Transmission Operation in Slave Mode
Reception in Slave Mode: Figure 17.12 shows an example of settings and operation for slave
mode reception.
Rev.1.50 Aug. 30, 2006 Page 626 of 860
REJ09B0288-0150