SH7713 Datasheet, PDF (381/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
12.4 Register Descriptions
The BSC has the following registers. Refer to section 23, List of Registers, for the addresses and
access size for these registers.
Do not access spaces other than CS0 until the termination of the setting the memory interface.
• Common control register (CMNCR)
• Bus control register for area 0 (CS0BCR)
• Bus control register for area 2 (CS2BCR)
• Bus control register for area 3 (CS3BCR)
• Bus control register for area 4 (CS4BCR)
• Bus control register for area 5A (CS5ABCR)
• Bus control register for area 5B (CS5BBCR)
• Bus control register for area 6A (CS6ABCR)
• Bus control register for area 6B (CS6BBCR)
• Wait control register for area 0 (CS0WCR)
• Wait control register for area 2 (CS2WCR)
• Wait control register for area 3 (CS3WCR)
• Wait control register for area 4 (CS4WCR)
• Wait control register for area 5A (CS5AWCR)
• Wait control register for area 5B (CS5BWCR)
• Wait control register for area 6A (CS6AWCR)
• Wait control register for area 6B (CS6BWCR)
• SDRAM control register (SDCR)
• Refresh timer control/status register (RTCSR)*¹
• Refresh timer counter (RTCNT)*¹
• Refresh time constant register (RTCOR)*¹
• SDRAM mode register for area 2 (SDMR2)*²
• SDRAM mode register for area 3 (SDMR3)*²
Notes: 1. This register only accepts 32-bit writing to prevent incorrect writing. In this case, the
upper 16 bits of the data must be H'A55A. Otherwise, writing cannot be performed. In
reading, the upper 16 bits are read as H'0000.
2. The contents of this register are stored in SDRAM. When this register space is
accessed, the corresponding register in SDRAM is written to. For details, see
description of Power-on Sequence in section 12.5.5, SDRAM Interface.
Rev.1.50 Aug. 30, 2006 Page 341 of 860
REJ09B0288-0150