SH7713 Datasheet, PDF (633/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W
4 to 0 
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
17.3.2 Serial Clock Select Register (SISCR)
SISCR is used to set the baud rate generator operation. SISCR can be specified when the TRMD1
and TRMD0 bits in SIMDR are specified as B′10 or B′11. SISCR is initialized by a power-on
reset or software reset.
Initial
Bit
Bit Name Value R/W
15
MSSEL 1
R/W
14
MSIMM 1
R/W
13
—
0
R
12
BRPS4 0
R/W
11
BRPS3 0
R/W
10
BRPS2 0
R/W
9
BRPS1 0
R/W
8
BRPS0 0
R/W
7 to 3 —
All 0 R
Description
Master Clock Source Selection
The master clock is the clock input to the baud rate
generator.
0: Uses the SIOMCLK pin input signal as the master clock
1: Uses PCLK as the master clock
Master Clock Direct Selection
0: Uses the baud rate generator output clock as the clock
source
1: Uses the master clock itself as the clock source
Reserved
This bit is always read as 0. The write value should always
be 0.
Baud Rate Generator’s Prescalar Setting (BRPS)
Set the master clock division ratio BRPS.
00000: (× 1/32)
00001: (× 1/1)
00010: (× 1/2)
11111: (× 1/31)
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev.1.50 Aug. 30, 2006 Page 593 of 860
REJ09B0288-0150