SH7713 Datasheet, PDF (209/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
DMA address error:
• Conditions
 Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
 Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n +
3)
• Types
Instruction asynchronous, processing-completion type
• Save address
An address of the instruction following the instruction where an exception occurs (a delayed
branch instruction destination address if an instruction is assigned to a delay slot)
• Exception code
H′5C0
• Remarks
An exception occurs when a DMA transfer is executed while an illegal instruction address
described above is specified in the DMAC. Since the DMA transfer is performed
asynchronously with the CPU instruction operation, an exception is also requested
asynchronously with the instruction execution. For details on the DMAC, refer to section 13,
Direct Memory Access Controller (DMAC).
4.3.3 General Exceptions (MMU Exceptions)
When the address translation unit of the memory management unit (MMU) is valid, MMU
exceptions are checked after a CPU address error has been checked. Four types of MMU
exceptions are defined: TLB miss exception, TLB invalid exception, TLB protection exception,
initial page write exception. These exceptions are checked in this order.
A vector offset for a TLB miss exception is defined as H′00000400 to simplify exception source
determination. For details on MMU exception operations, refer to section 5, Memory Management
Unit (MMU).
TLB miss exception:
• Conditions
Comparison of TLB addresses shows no address match.
• Types
Instruction synchronous, re-execution type
Rev.1.50 Aug. 30, 2006 Page 169 of 860
REJ09B0288-0150