SH7713 Datasheet, PDF (257/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 6 Cache
6.2 Register Descriptions
The cache has the following registers. For details on register addresses and register states during
each process, refer to section 23, List of Registers.
• Cache control register 1 (CCR1)
• Cache control register 2 (CCR2)
• Cache control register 3 (CCR3)
6.2.1 Cache Control Register 1 (CCR1)
The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has a CF bit (which
invalidates all cache entries), and WT and CB bits (which select either write-through mode or
write-back mode). Programs that change the contents of the CCR1 register should be placed in
address space that is not cached.
Bit
31 to 4
3
2
1
Bit Name
—
Initial
Value
All 0
CF
0
CB
0
WT
0
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Cache Flush
Writing 1 flushes all cache entries (clears the V, U,
and LRU bits of all cache entries to 0). This bit is
always read as 0. Write-back to external memory is
not performed when the cache is flushed.
Write-Back
Indicates the cache’s operating mode for space P1.
0: Write-through mode
1: Write-back mode
Write-Through
Indicates the cache’s operating mode for spaces P0,
U0, and P3.
0: Write-back mode
1: Write-through mode
Rev.1.50 Aug. 30, 2006 Page 217 of 860
REJ09B0288-0150