SH7713 Datasheet, PDF (291/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
8.4.4 Interrupt Request Register 0 (IRR0)
IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ5 to IRQ0.
This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in
standby mode.
Bit
Bit Name Initial Value R/W Description
7

0
R
Reserved
6

0
R
These bit are always read as 0. The write value
should always be 0.
5
IRQ5R
0
R/W IRQn Interrupt Request
4
IRQ4R
0
3
IRQ3R
0
2
IRQ2R
0
1
IRQ1R
0
0
IRQ0R
0
R/W Indicates whether there is interrupt request input
R/W ^{to the IRQn pin. When edge-detection mode is}
set for IRQn, an interrupt request is cleared by
R/W _{writing 0 to the IRQnR bit after reading IRQnR =}
R/W ^1.
R/W When level-detection mode is set for IRQn, an
interrupt request is set/cleared by only 1/0 input
to the IRQn pin.
IRQnR
0: No interrupt request input to IRQn pin
1: Interrupt request input to IRQn pin
Legend: n = 0 to 5
8.4.5 Interrupt Request Register 1 (IRR1)
IRR1 is an 8-bit register that indicates whether interrupt requests from the DMAC and the SCIF0
are generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
Bit
Bit Name Initial Value R/W Description
7
TXI0R
0
R
TXI0 Interrupt Request
Indicates whether the TXI0 (SCIF0) interrupt
request is generated.
0: TXI0 interrupt request is not generated
1: TXI0 interrupt request is generated
Rev.1.50 Aug. 30, 2006 Page 251 of 860
REJ09B0288-0150