SH7713 Datasheet, PDF (624/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state the input from the RxD pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set.
Although the SCIF stops transferring receive data to SCFRDR after receiving a break, the receive
operation continues.
Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous
mode, the SCIF operates on a base clock with a frequency of 16 times the transfer rate.
In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the
base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is
shown in figure 16.19.
Base clock
Receive data
(RxD)
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
–7.5 clocks
+7.5 clocks
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 16.19 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M = 0.5 – ¹ – (L – 0.5)F – ^{D – 0.5} (1 + F) × 100% ..................... (1)
2N
N
M:
Receive margin (%)
N:
Ratio of clock frequency to bit rate (N = 16)
D:
Clock duty cycle (D = 0 to 1.0)
L:
Frame length (L = 9 to 12)
F:
Absolute deviation of clock frequency
Rev.1.50 Aug. 30, 2006 Page 584 of 860
REJ09B0288-0150