SH7713 Datasheet, PDF (148/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Table 3.15 Source Register in DSP Operations
Guard Bits
Register Bits
Registers Instructions
39
32 31
16 15
0
A0, A1
DSP
Fixed-point, PDMSB,
operation PSHA
40-bit data
Integer
24-bit data
Logical, PSHL, PMULS
16-bit data
Data
transfer
MOVX/Y.W, MOVS.W
MOVS.L
16-bit data
32-bit data
A0G, A1G Data
transfer
MOVS.W
MOVS.L
Data
Data
X0, X1
Y0, _Y1
M0, M1
DSP
operation
Fixed-point, PDMSB,
PSHA
Integer
Sign*
Sign*
32-bit data
16-bit data
Logical, PSHL, PMULS
16-bit data
Data
transfer
MOVS.W
MOVS.L
16-bit data
32-bit data
Note: * The data is sign-extended and input to the ALU.
The DSP unit incorporates one control register and DSP status register (DSR). The DSR register
stores the DSP data operation result (zero, negative, others). The DSP register also has the DC bit
whose function is similar to the T bit of the CPU register. The DC bit functions as status flag.
Conditional DSP data operations are controlled based on the DC bit. These operation control
affects only the DSP unit instructions. In other words, these operations control affects only the
DSP registers and does not affect address register update and CPU instructions such as load and
store instructions. A condition to be reflected on the DC bit should be specified to the DC status
selection bits (CS[2:0]).
The unconditional DSP type data instructions other than PMULS, MOVX, MOVY, and MOVS
change the condition flag and DC bit. However, the CPU instructions including the MAC
instruction do not modify the DC bit. In addition, conditional DSP instructions do not modify the
DSR.
Rev.1.50 Aug. 30, 2006 Page 108 of 860
REJ09B0288-0150