SH7713 Datasheet, PDF (867/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 Electrical Characteristics
CKIO
A25 to A0
A12/A11^*1
Tp
Tpw
Trr
Trc
t_AD3
t_AD3
t_AD3
t_AD3
CSn
RD/WR
RAS
CAS
t_CSD2
t_CSD2
t_CSD2
t_CSD2
t_RWD2
t_RWD2
t_RASD2
t_RASD2
t_RASD2
t_RASD2
t_CASD2
t_CASD2
DQMxx
D31 to D0
(Hi-Z)
Trc
Trc
Trc
Trc
t_RWD2
BS
CKE
t_CKED2
t_CKED2
DACKn*²
Notes: 1. Address pin to be connected to A10 of SDRAM.
2. DACKn is a waveform when active-low is specified.
Figure 24.46 Synchronous DRAM Self-Refresh Timing
(TRP = 2 Cycle, Low-Frequency Mode)
Rev.1.50 Aug. 30, 2006 Page 827 of 860
REJ09B0288-0150