SH7713 Datasheet, PDF (219/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
MMU Exception in Repeat Control Period: If an MMU exception occurs in the repeat control
period, a specific exception code is generated as well as a CPU address error. For a TLB miss
exception, TLB invalid exception, and initial page write exception, an exception code (H′070) is
specified in the EXPEVT. For a TLB protection exception, an exception code (H′0D0) is specified
in the EXPEVT. In a TLB miss exception, vector offset is specified as H′00000100.
An instruction where an exception occurs and the SPC value to be saved are the same as those for
the CPU address error.
After this exception processing, the repeat control cannot be returned correctly. To execute a
repeat loop correctly, care must be taken not to generate an MMU related exception in the repeat
control period.
Note:
In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
detection instructions and all the remaining instructions. In a repeat loop consisting of four
or more instructions, restrictions apply to only the four instructions that include a repeat
end instruction. The restriction occurs when SR.RC[11:0] ≥ 1.
4.5 Usage Notes
1. An instruction assigned at a delay slot of the RTE instruction is executed after the contents of
the SSR is restored into the SR. An acceptance of an exception related to instruction access is
determined according to the SR before restore. An acceptance of other exceptions is
determined by processing mode of the SR after restore, and BL bit value. A processing-
completion type exception is accepted before an instruction at the RTE branch destination
address is executed. However, note that the correct operation cannot be guaranteed if a re-
execution type exception occurs.
2. In an instruction assigned at a delay slot of the RTE instruction, a user break cannot be
accepted.
3. If the MD and BL bits of the SR register are changed by the LDC instruction, an exception is
accepted according to the changed SR value from the next instruction.* A processing-
completion type exception is accepted after the next instruction is executed. An interrupt and
DMA address error in re-execution type exceptions are accepted before the next instruction is
executed.
Note: * If an LDC instruction is executed for the SR, the following instructions are re-fetched
and an instruction fetch exception is accepted according to the modified SR value.
Rev.1.50 Aug. 30, 2006 Page 179 of 860
REJ09B0288-0150