SH7713 Datasheet, PDF (157/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

DSP type fixed point
39
With guard bits S
Without guard bits
39
Multiplier input
31 30
31 30
S
31 30
S
DSP type integer
39
With guard bits S
32 31
31
Without guard bits
S
Shift amount for
31
arithmetic shift (PSHA)
Shift amount for
31
logical shift (PSHL)
16 15
16 15
16 15
22 16 15
S
21 16 15
S
DSP type logical
CPU type integer
Longword
39
31
31
S
16 15
Section 3 DSP Operating Unit
0
–2⁸ to +2⁸ – 2^–31
0
–1 to +1 – 2^–31
0
–1 to +1 – 2^–15
0
–2²³ to +2²³ – 1
0
–2¹⁵ to +2¹⁵ – 1
0
–32 to +32
0
–16 to +16
0
0
–2³¹ to +2³¹ – 1
S: Sign bit
: Binary point
: Does not affect the operations
Figure 3.8 Data Formats
The shift amount for the arithmetic shift (PSHA) instruction has a 7-bit field that can represent
values from –64 to +63, but –32 to +32 are valid numbers for the instruction. Also the shift
amount for a logical shift operation has a 6-bit field, but –16 to +16 are valid numbers for the
instruction. The results when an invalid shift amount is specified cannot be guaranteed.
Rev.1.50 Aug. 30, 2006 Page 117 of 860
REJ09B0288-0150