SH7713 Datasheet, PDF (86/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Addressing
Mode
Instruction
Format Effective Address Calculation Method
Register
@–Rn
indirect with
pre-decrement
Effective address is register Rn
contents, decremented by a constant
beforehand: 1 for a byte operand, 2 for a
word operand, 4 for a longword
operand.
Rn
Rn - 1/2/4
-
Rn - 1/2/4
Register
indirect with
displacement
@(disp:4,
Rn)
1/2/4
Effective address is register Rn contents
with 4-bit displacement disp added. After
disp is zero-extended, it is multiplied by
1 (byte), 2 (word), or 4 (longword),
according to the operand size.
Rn
disp
(zero-extended)
+
×
Rn
+ disp × 1/2/4
Calculation Formula
Byte: Rn – 1 → Rn
Word: Rn – 2 → Rn
Longword: Rn – 4 → Rn
(Instruction executed with
Rn after calculation)
Byte: Rn + disp
Word: Rn + disp × 2
Longword: Rn + disp × 4
1/2/4
Indexed
@(R0, Rn) Effective address is sum of register Rn
register indirect
and R0 contents.
Rn
+
Rn + R0
R0
GBR indirect
with
displacement
@(disp:8,
GBR)
Effective address is register GBR
contents with 8-bit displacement disp
added. After disp is zero-extended, it is
multiplied by 1 (byte), 2 (word), or 4
(longword), according to the operand
size.
GBR
disp
+
(Zero-extended)
×
GBR
+ disp × 1/2/4
1/2/4
Rn + R0
Byte: GBR + disp
Word: GBR + disp × 2
Longword: GBR + disp ×
4
Rev.1.50 Aug. 30, 2006 Page 46 of 860
REJ09B0288-0150