SH7713 Datasheet, PDF (580/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
3
STOP
0
R/W Stop Bit Length
Selects 1 or 2 bits as the stop bit length. The STOP
bit setting is only valid in asynchronous mode. When
clock synchronous mode is set, the STOP bit setting
is invalid since stop bits are not added.
0: 1 stop bit*¹
1: 2 stop bits*²
Notes: 1. In transmission, a single 1-bit (stop bit) is
added to the end of a transmit character
before it is sent.
2. In transmission, two 1-bits (stop bits) are
added to the end of a transmit character
before it is sent.
In reception, only the first stop bit is checked,
regardless of the STOP bit setting. If the second stop
bit is 1, it is treated as a stop bit; if it is 0, it is treated
as the start bit of the next transmit character.
2

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
1
CKS1
0
R/W Clock Select 1 and 0
0
CKS0
0
R/W Select the clock source for the on-chip baud rate
generator.
00: Pφ
01: Pφ/4
10: Pφ/16
11: Pφ/64
Rev.1.50 Aug. 30, 2006 Page 540 of 860
REJ09B0288-0150