SH7713 Datasheet, PDF (488/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
This LSI
A25 to A0
D7 to D0
D15 to D8
RD/WR
CE1A
CE2A
RD
WE
ICIORD
ICIOWR
I/O Port
WAIT
IOIS16
G
G
DIR
G
DIR
G
Card
detection
circuit
PC card
(memory I/O)
A25 to A0
D7 to D0
D15 to D8
CE1
CE2
OE
WE/PGM
IORD
IOWR
REG
WAIT
IOIS16
CD1,CD2
Figure 12.38 Example of PCMCIA Interface Connection
Basic Timing for Memory Card Interface: Figure 12.39 shows the basic timing of the PCMCIA
IC memory card interface. If areas 5 and 6 in the physical space are specified as the PCMCIA
interface, accessing the common memory areas in areas 5 and 6 automatically accesses the IC
memory card interface. If the external bus frequency (CKIO) increases, the setup times and hold
times for the address pins (A25 to A0) to RD and WE, card enable signals (CE1A, CE2A, CE1B,
CE2B), and write data (D15 to D0) become insufficient. To prevent this error, the LSI can specify
the setup times and hold times for areas 5 and 6 in the physical space independently, using
CS5BWCR and CS6BWCR. In the PCMCIA interface, as in the normal space interface, a
software wait or hardware wait can be inserted using the WAIT pin. Figure 12.40 shows the
PCMCIA memory bus wait timing.
Rev.1.50 Aug. 30, 2006 Page 448 of 860
REJ09B0288-0150