SH7713 Datasheet, PDF (245/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Memory Management Unit (MMU)
5.5 MMU Exceptions
When the address translation unit of the MMU is enabled, occurrence of the MMU exception is
checked following the CPU address error check. There are four MMU exceptions: TLB miss, TLB
protection violation, TLB invalid, and initial page write, and these MMU exceptions are checked
in this order.
5.5.1 TLB Miss Exception
A TLB miss results when the virtual address and the address array of the selected TLB entry are
compared and no match is found. TLB miss exception processing includes both hardware and
software operations.
Hardware Operations: In a TLB miss, this hardware executes a set of prescribed operations, as
follows:
1. The VPN field of the virtual address causing the exception is written to the PTEH register.
2. The virtual address causing the exception is written to the TEA register.
3. Either exception code H'040 for a load access, or H'060 for a store access, is written to the
EXPEVT register.
4. The PC value indicating the address of the instruction in which the exception occurred is
written to the save program counter (SPC). If the exception occurred in a delay slot, the PC
value indicating the address of the related delayed branch instruction is written to the SPC.
5. The contents of the status register (SR) at the time of the exception are written to the save
status register (SSR).
6. The MD bit in SR is set to 1 to place the privileged mode.
7. The BL bit in SR is set to 1 to mask any further exception requests.
8. The RB bit in SR is set to 1.
9. The RC field in the MMU control register (MMUCR) is incremented by 1 when all entries
indexed are valid. When some entries indexed are invalid, the smallest way number of them is
set in RC.
10. Execution branches to the address obtained by adding the value of the VBR contents and
H'00000400 to invoke the user-written TLB miss exception handler.
Software (TLB Miss Handler) Operations: The software searches the page tables in external
memory and allocates the required page table entry. Upon retrieving the required page table entry,
software must execute the following operations:
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